1. Field of the Invention
The present invention is related to circuit design and more particularly to chip design systems and computer aided design (CAD) systems for designing printed circuits, integrated circuits (ICs) and IC chips.
2. Background Description
A typical integrated circuit (IC) chip includes a stack of several sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and wires that connect the devices into circuits. Typical such connections are through vertical inter-level interconnects such as a device contact, e.g., to diffusion or a gate, or what is known as a via between wiring levels. Each of these layers of shapes, also known as mask levels or just levels, may be created or printed optically through well known photolithographic masking, photo-developing and level definition techniques, e.g., etching, implanting, deposition and etc. Ideally, fabrication parameters such as process biases, applied to features on a particular layer, affect all features on that layer uniformly. However, all features do not respond uniformly.
While ideally contacts and vias have zero resistance, each contact or via has an inherent resistance that is inversely proportional to contact/via size and what is referred to as the its leading edge. For a typical non-critical signal line driving a capacitive load (C), even several picofarads (pf), a contact/via that adds tens and perhaps hundreds of Ohms (Ω) of contact resistance (R) to the signal path, adds delay (RC) to the path that may be neglectable. So typically, minimum dimension contacts and vias are used in non-critical signal paths. However, where relatively large currents flow through such a contact/via, this same contact resistance can cause relatively large voltage drops or voltage spikes (e.g., 20% of the supply voltage or more) that are very troublesome. The simplest way to reduce contact resistance is to make the contacts and vias larger. Unfortunately, different sized contact shapes and vias behave differently to focus and subsequent fabrication processing.
When small, minimum dimension shapes print and etch to form desired contacts or vias, large shapes for larger contacts tend to expand. The design shape washes out and, perhaps, encroaches on neighboring circuits or may at least be larger than the adjacent layer (above and below) shapes being connected, i.e., having inadequate coverage. Consequently, this encroachment may cause unwanted shorts to those neighboring circuits or wiring. By contrast, when the larger shapes are the target for printing and etching, the smaller, minimum dimension shapes may not open (i.e., contacts or vias may fail to form). Consequently, resulting circuits may have open signal lines. Either result is undesirable, causing chips to fail and reducing chip yield. Either of these results is undesirable and may cause failing chips, i.e., yield loss.
Typically, to avoid either extreme and the resulting yield loss, contacts and vias are constrained to a single size across an entire design. For example, contact/via shapes may be constrained all one, e.g., minimum dimension, with larger contacts/vias being replaced with an array of these smaller shapes on a minimum pitch.
U.S. Pat. No. 7,536,664, “Physical Design System And Method” to Cohn et al., teaches a circuit design format that is now known as gridded glyph geometric objects (L3GO) format. In particular, a L3GO layout is, essentially, an extension to a conventional design with few optional conventional shapes, but primarily much simpler L3GO-specific components, i.e., grids, glyphs and attributes, on a much more coarse grid. The grid is a regular rectangular array of points, all of which are subsets of a built-in manufacturing grid. Each glyph is specified with respect to the grid and assigned to a layer, e.g., by attributes. Also, attributes assigned to each glyph may carry arbitrary additional information including, for example, design intent, e.g., indicating that a polysilicon level glyph is in a timing-critical net.
Generally, typical L3GO layouts include three simple geometric types of primitives or glyphs, point glyphs (also referred to herein as points), stick glyphs (also referred to herein as sticks) and rectangle glyphs (also referred to herein as rectangles). Point glyphs are dimensionless or 0-dimensional points lying at grid points and are typically used for vertical interconnections, e.g., contacts and vias. Stick glyphs are 1-dimensional line segments drawn between two grid points. Typically, stick glyphs are used for FET gates or for interconnections. Rectangle glyphs are 2-dimensional, axis-aligned rectangles with vertices on grid points, typically used for diffusion regions. As with polygonal shapes in conventional layouts, each L3GO glyph resides on a particular design layer (e.g., POLY, DIFF), which indicates its function, wafer material and etc.
Unfortunately, using a point glyph alone (e.g., a point on a via layer) to represent vias, especially using multiple, redundant vias forming a single connection, has been ineffective in capturing design intent. Adding an array of point glyphs that may not allow a minimum pitch array has not proven effective either.
Thus, there is a need for design tools that efficiently locate arrays of contacts or vias in a typical circuit design.